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| September 2006 HYB18L256160B[C/F]-7.5 HYE18L256160B[C/F]-7.5 HYE18L256160BCL-7.5 HYE18L256160BFL-7.5 DRAMs for Mobile Applications 256-Mbit Mobile-RAM Data S heet Rev. 1.73 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM HYB18L256160B[C/F]-7.5, HYE18L256160B[C/F]-7.5, HYE18L256160BCL-7.5, HYE18L256160BFL-7.5 Revision History: 2006-09, Rev. 1.73 Page All Subjects (major since last revision) Qimonda update added disclaimer 53 29 8 12 42 15, 29, 50 Rev. 1.71: deleted -BCX and BFX product types Table 25: Updated Chapter 2.1: added to note 6: Programming of the Extended Mode Register... Extended Mode Register table: Editorial changes Chapter 2.2.1.6: Editorial change Chapter 2.4.9.2: replaced last paragraph by: If during normal operation... Table 9, Table 13 and Table 26: tIH changed Table 26: note 7 changed: If tT > 1ns, a value of [0.5 x (tT -1)] ns... Table 25: editorial changes Previous Revision: Rev. 1. 61 Previous Revision: 2005-07, Rev. 1.72 Previous Revision: Rev. 1.6 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 01302004-CZ2R-J9SE 2 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 1 1.1 * * * * * * * * * * * * Overview Features 4 banks x 4 Mbit x 16 organization Fully synchronous to positive clock edge Four internal banks for concurrent operation Programmable CAS latency: 2, 3 Programmable burst length: 1, 2, 4, 8 or full page Programmable wrap sequence: sequential or interleaved Programmable drive strength Auto refresh and self refresh modes 8192 refresh cycles / 64 ms Auto precharge Commercial (0C to +70C) and Extended (-25C to +85C) operating temperature range 54-ball P-VFBGA package (12.0 x 8.0 x 1.0 mm) Power Saving Features * * * * * Low supply voltages: VDD = 1.65V to 1.95V, VDDQ = 1.65V to 1.95V Optimized self refresh (IDD6) and standby currents (IDD2 / IDD3) Programmable Partial Array Self Refresh (PASR) Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor Power-Down and Deep Power Down modes TABLE 1 Performance Part Number Speed Code Speed Grade Access Time (tACmax) Clock Cycle Time (tCKmin) CL = 3 CL = 2 CL = 3 CL = 2 - 7.5 133 5.4 6.0 7.5 9.5 Unit MHz ns ns ns ns TABLE 2 Memory Addressing Scheme Item Banks Rows Columns Addresses BA0, BA1 A0 - A12 A0 - A8 Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 3 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM TABLE 3 Ordering Information Type 1) Description Package Commercial Temperature Range HYB18L256160B[C/F] HYB18L256160B[C/F] 133 MHz 4 Banks x 4 Mbit x 16 LP-SDRAM P-VFBGA-54-2 133 MHz 4 Banks x 4 Mbit x 16 LP-SDRAM P-VFBGA-54-2 Extended Temperature Range HYB18L256160BC-7.5 HYB18L256160BCL-7.5 HYB18L256160BF-7.5 HYB18L256160BFL-7.5 133 MHz 4 Banks x 4 Mbit x 16 LP-SDRAM P-VFBGA-54-2 133 MHz 4 Banks x 4 Mbit x 16 LP-SDRAM P-VFBGA-54-2 133 MHz 4 Banks x 4 Mbit x 16 LP-SDRAM P-VFBGA-54-2 133 MHz 4 Banks x 4 Mbit x 16 LP-SDRAM 1) HY[B/E]: Designator for memory products (HYB: Standard temp. range; HYE: extended temp. range) 18L: 1.8 V Mobile-RAM 256: 256 MBit density 160: 16 bit interface width B: die revision C / F: lead-containing product (C) / green product (F) L: low-power product -7.5: speed grade(s): min. clock cycle time 1.2 Pin Configuration FIGURE 1 Standard Ballout 256-Mbit Mobile-RAM Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 4 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 1.3 Description The HY[B/E]18L256160B[C/F]L is especially designed for mobile applications. It operates from a 1.8 V power supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR). A conventional data-retaining Power Down (PD) mode is available as well as a non-data-retaining Deep Power Down (DPD) mode. The HY[B/E]18L256160B[C/F]L is housed in a 54-ball PVFBGA package. It is available in Commercial (0 C to +70 C) and Extended (-25 C to +85 C) temperature ranges. The HY[B/E]18L256160B[C/F]L is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The HY[B/E]18L256160B[C/F]L achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are burstoriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4, 8 or full page) in a programmed sequence. The device operation is fully synchronous: all inputs are registered at the positive edge of CLK. FIGURE 2 Functional Block Diagram Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 5 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 1.4 Pin Definition and Description TABLE 4 Pin Description Ball CLK CKE Type Input Input Detailed Function Clock: all inputs are sampled on the positive edge of CLK. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or SUSPEND (access in progress). CKE is synchronous for POWER-DOWN entry and exit and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers, excluding CLK and CKE are disabled during power-down. Input buffers, excluding CKE are disabled during SELF REFRESH. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple memory banks. CS is considered part of the command code. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Data Inputs/Output: Bi-directional data bus (16 bit) Input/Output Mask: input mask signal for WRITE cycles and output enable for READ cycles. For WRITEs, DQM acts as a data mask when HIGH. For READs, DQM acts as an output enable and places the output buffers in High-Z state when HIGH (two clocks latency). LDQM corresponds to the data on DQ0 - DQ7; UDQM to the data on DQ8 - DQ15. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or PRECHARGE command is being applied. BA0, BA1 also determine which mode register is to be loaded during a MODE REGISTER SET command (MRS or EMRS). Address Inputs: A0 - A12 define the row address during an ACTIVE command cycle. A0 - A8 define the column address during a READ or WRITE command cycle. In addition, A10 (= AP) controls Auto Precharge operation at the end of the burst read or write cycle. During a PRECHARGE command, A10 (= AP) in conjunction with BA0, BA1 controls which bank(s) are to be precharged: if A10 is HIGH, all four banks will be precharged regardless of the state of BA0 and BA1; if A10 is LOW, BA0, BA1 define the bank to be precharged. During MODE REGISTER SET commands, the address inputs hold the op-code to be loaded. I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity: VDDQ = 1.65V to 1.95V I/O Ground Power Supply: Power for the core logic and input buffers, VDD = 1.65V to 1.95V Ground No Connect CS Input RAS, CAS, WE DQ0 - DQ15 LDQM, UDQM Input I/O Input BA0, BA1 Input A0 - A12 Input VDDQ VSSQ VDD VSS N.C. Supply Supply Supply Supply - Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 6 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2 Functional Description The 256-Mbit Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the Mobile-RAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 7 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.1 Power On and Initialization The Mobile-RAM must be powered up and initialized in a predefined manner (see Figure 3). Operational procedures other than those specified may result in undefined operation. FIGURE 3 Power-Up Sequence and Mode Register Sets 1. At first, device core power (VDD) and device IO power (VDDQ) must be brought up simultaneously. Typically VDD and VDDQ are driven from a single power converter output. Assert and hold CKE and DQM to a HIGH level. 2. After VDD and VDDQ are stable and CKE is HIGH, apply stable clocks. 3. Wait for 200s while issuing NOP or DESELECT commands. 4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least tRP period. 5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least tRFC period. 6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode Register, each followed by NOP or DESELECT commands for at least tMRD period; the order in which both registers are programmed is not important. Programming of the Extended Mode Register may be omitted when default values (half drive strength, 4 bank refresh) will be used. Following these steps, the Mobile-RAM is ready for normal operation. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 8 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.2 Register Definition 2.2.1 Mode Register The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes the selection of a burst length (bits A0-A2), a burst type (bit A3), a CAS latency (bits A4-A6), and a write burst mode (bit A9). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. TABLE 5 Mode Register Definition (BA[1:0] = 00B) Field WB Bits 9 Type w Description Write Burst Mode 0B Burst Write 1B Single Write CAS Latency 010B 2 011B 3 Note: All other bit combinations are RESERVED. Burst Type 0B Sequential 1B Interleaved Burst Length 000B 1 001B 2 010B 4 011B 8 111B full page (Sequential burst type only) Note: All other bit combinations are RESERVED. CL [6:4] w BT 3 w BL [2:0] w Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 9 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.2.1.1 Burst Length READ and WRITE accesses to the Mobile-RAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, 8 locations are available for both the sequential and interleaved burst types, and a full-page burst mode is available for the sequential burst type. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-A8 when the burst length is set to two, by A2-A8 when the burst length is set to four and by A3-A8 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full page bursts wrap within the page if the boundary is reached. Please note that full page bursts do not self-terminate; this implies that full-page read or write bursts with Auto Precharge are not legal commands. TABLE 6 Burst Definition Burst Length Starting Column Address A2 2 4 0 0 1 1 8 0 0 0 0 1 1 1 1 Full Page Notes 1. 2. 3. 4. 5. For a burst length of 2, A1-Ai select the two-data-element block; A0 selects the first access within the block. For a burst length of 4, A2-Ai select the four-data-element block; A0-A1 select the first access within the block. For a burst length of 8, A3-Ai select the eight-data-element block; A0-A2 select the first access within the block. For a full page burst, A0-Ai select the starting data element. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the block. n 0 0 1 1 0 0 1 1 n A1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 n Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2, ... Order of Accesses Within a Burst Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 not supported Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 10 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.2.1.2 Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6. 2.2.1.3 Read Latency The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available with clock edge n + m (for details please refer to the READ command description). 2.2.1.4 Write Burst Mode When A9 = 0, the burst length programmed via A0-A2 applies to both read and write bursts; when A9 = 1, write accesses consist of single data elements only. 2.2.1.5 Extended Mode Register The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh (PASR, bits A0-A2)), the Temperature Compensated Self Refresh (TCSR, bits A3-A4)) and the drive strength selection for the DQs (bits A5-A6). The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. TABLE 7 Extended Mode Register Definition (BA[1:0] = 10B) Field DS Bits [6:5] Type w Description Selectable Drive Strength Full Drive Strength 00B 01B Half Drive Strength (default) Note: All other bit combinations are RESERVED. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 11 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM Field TCSR PASR Bits [4:3] [2:0] Type w w Description Temperature Compensated Self Refresh XXB Superseded by on-chip temperature sensor (see text) Partial Array Self Refresh 000B all banks (default) 001B 1/2 array (BA1 = 0) 010B 1/4 array (BA1 = BA0 = 0) 101B 1/8 array (BA1 = BA0 = RA12 = 0) 110B 1/16 array (BA1 = BA0 = RA12 = RA11 = 0) Note: All other bit combinations are RESERVED. 2.2.1.6 Partial Array Self Refresh (PASR) Partial Array Self Refresh is a power-saving feature specific to Mobile RAMs. With PASR, self refresh may be restricted to variable portions of the total array. The selection comprises all four banks (default), two banks, one bank, half of one bank, and a quarter of one bank. Data written to the non activated memory sections will get lost after a period defined by tREF (cf. Table 15). 2.2.1.7 Temperature Compensated Self Refresh (TCSR) DRAM devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain the stored information. This refresh requirement heavily depends on the die temperature: high temperatures correspond to short refresh periods, and low temperatures correspond to long refresh periods. The Mobile-RAM is equipped with an on-chip temperature sensor which continuously senses the actual die temperature and adjusts the refresh period in Self Refresh mode accordingly. This makes any programming of the TCSR bits in the Extended Mode Register obsolete. It also is the superior solution in terms of compatibility and power-saving, because * it is fully compatible to all processors that do not support the Extended Mode Register * it is fully compatible to all applications that only write a default (worst case) TCSR value, e.g. because of the lack of an external temperature sensor * it does not require any processor interaction for regular TCSR updates 2.2.1.8 Selectable Drive Strength The drive strength of the DQ output buffers is selectable via bits A5 and A6 and shall be set load dependent. The half drive strength is suitable for typical Mobile-RAM applications. The full drive strength is intended for heavier loaded systems. I-V curves for full drive strength and half drive strength can be found in Table 29. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 12 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.3 State Diagram FIGURE 4 State Diagram Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 13 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4 Commands TABLE 8 Command Overview Command NOP ACT RD WR BST PRE ARF MRS - - DESELECT NO OPERATION ACTIVE (Select bank and row) READ (Select bank and column and start read burst) WRITE (Select bank and column and start write burst) BURST TERMINATE or DEEP POWER DOWN PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (enter self refresh mode) MODE REGISTER SET Data Write / Output Enable Write Mask / Output Disable (High-Z) CS RAS H L L L L L L L L - - X H L H H H L L L - - CAS WE DQM X H H L L H H L L - - X H H H L L L H L - - X X X L/H L/H X X X X L H X X Bank / Row Bank / Col Bank / Col X Code X Op-Code - - Address Note 1) 1) 2) 3) 3) 4) 5) 6)7) 8) 9) 9) 1) DESELECT and NOP are functionally interchangeable. 2) BA0, BA1 provide bank address, and A0 - A12 provide row address. 3) BA0, BA1 provide bank address, A0 - A8 provide column address; A10 HIGH enables the Auto Precharge feature (non persistent), A10 LOW disables the Auto Precharge feature. 4) This command is BURST TERMINATE if CKE is HIGH, DEEP POWER DOWN if CKE is LOW. The BURST TERMINATE command is defined for READ or WRITE bursts with Auto Precharge disabled only. 5) A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are "Don't Care". 6) This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7) Internal refresh counter controls row and bank addressing; all inputs and I/Os are "Don't Care" except for CKE. 8) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other combinations of BA0, BA1 are reserved; A0 - A12 provide the op-code to be written to the selected mode register. 9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read cycles; DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; DQ output buffers are placed in High-Z state (two clocks latency) during read cycles. Address (A0 - A12, BA0, BA1), write data (DQ0 - DQ15) and command inputs (CKE, CS, RAS, CAS, WE, DQM) are all registered on the positive edge of CLK. Figure 5 shows the basic timing parameters, which apply to all commands and operations. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 14 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM FIGURE 5 Address / Command Inputs Timing Parameters TABLE 9 Inputs Timing Parameters Parameter Symbol min. Clock cycle time Clock frequency Clock high-level width Clock low-level width Address and command input setup time Address and command input hold time CL = 3 CL = 2 CL = 3 CL = 2 - 7.5 max. -- -- 133 105 -- -- -- -- ns ns MHz MHz ns ns ns ns -- -- -- -- -- -- Unit Note tCK fCK tCH tCL tIS tIH 7.5 9.5 -- -- 2.5 2.5 1.5 0.5 Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 15 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.1 NO OPERATION (NOP) FIGURE 6 No operation Command The NO OPERATION (NOP) command is used to perform a NOP to a Mobile-RAM which is selected (CS = LOW). This prevents unwanted commands from being registered during idle states. Operations already in progress are not affected. 2.4.2 DESELECT The DESELECT function (CS = HIGH) prevents new commands from being executed by the Mobile-RAM. The Mobile-RAM is effectively deselected. Operations already in progress are not affected. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 16 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.3 MODE REGISTER SET FIGURE 7 Mode Register Set Command The Mode Register and Extended Mode Register are loaded via inputs A0 - A12 (see mode register descriptions in Chapter 2.2). The MODE REGISTER SET command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met. FIGURE 8 Mode Register Definition TABLE 10 Timing Parameters for Mode Register Set Command Parameter Symbol min. MODE REGISTER SET command period - 7.5 max. -- Units Note tMRD 2 tCK -- Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 17 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.4 ACTIVE FIGURE 9 ACTIVE command Before any READ or WRITE commands can be issued to a bank within the Mobile-RAM, a row in that bank must be "opened" (activated). This is accomplished via the ACTIVE command and addresses A0 - A12, BA0 and BA1 (see Figure 9), which decode and select both the bank and the row to be activated. After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. FIGURE 10 Bank Activate Timings TABLE 11 Timing Parameters for ACTIVE Command Parameter Symbol min. ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE bank A to ACTIVE bank B delay - 7.5 max. -- -- -- ns ns ns 1) 1) 1) Units Note tRC tRCD tRRD 67 19 15 1) These parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 18 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.5 READ FIGURE 11 READ Command Subsequent to programming the mode register with CAS latency and burst length, READ bursts are initiated with a READ command, as shown in Figure 11. Basic timings for the DQs are shown in Figure 12; they apply to all read operations and therefore are omitted from all subsequent timing diagrams. The starting column and bank addresses are provided with the READ command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row being accessed starts precharge at the completion of the burst, provided tRAS has been satisfied. For the generic READ commands used in the following illustrations, Auto Precharge is disabled. FIGURE 12 Basic READ Timing Parameters for DQs Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 19 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM TABLE 12 Timing Parameters for READ Parameter Symbol min. Access time from CLK DQ low-impedance time from CLK DQ high-impedance time from CLK Data out hold time DQM to DQ High-Z delay (READ Commands) ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE to PRECHARGE command period PRECHARGE command period CL = 3 CL = 2 - 7.5 max. 5.4 6.0 -- 7.0 -- 2 -- -- 100k -- ns ns ns ns ns -- -- 1) 1) 1) 1) Units Note tAC tAC tLZ tHZ tOH tDQZ tRC tRCD tRAS tRP -- -- 1.0 3.0 2.5 -- 67 19 45 19 -- -- tCK ns ns ns ns 1) These parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. During READ bursts, the valid data-out element from the starting column address is available following the CAS latency after the READ command. Each subsequent data-out element is valid nominally at the next positive clock edge. Upon completion of a READ burst, assuming no other READ command has been initiated, the DQs go to High-Z state. Figure 13 and Figure 14 show single READ bursts for each supported CAS latency setting. FIGURE 13 Single READ Burst (CAS Latency = 2) Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 20 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM FIGURE 14 Single READ Burst (CAS Latency = 3) Data from any READ burst may be concatenated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. A READ command can be initiated on any clock cycle following a previous READ command, and may be performed to the same or a different (active) bank. The first data element from the new burst follows either the last element of a completed burst (Figure 15) or the last desired data element of a longer burst which is being truncated (Figure 16). The new READ command should be issued x cycles after the first READ command, where x equals the number of desired data elements. FIGURE 15 Consecutive READ Bursts Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 21 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM FIGURE 16 Random READ Bursts Non-consecutive READ bursts are shown in Figure 17. FIGURE 17 Non-Consecutive READ Bursts Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 22 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.5.1 READ Burst Termination Data from any READ burst may be truncated using the BURST TERMINATE command (see Page 36), provided that Auto Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the BURST TERMINATE command must be issued x clock cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency for READ bursts minus 1. This is shown in Figure 18. The BURST TERMINATE command may be used to terminate a full-page READ which does not self-terminate. FIGURE 18 Terminating a READ Burst Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 23 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.5.2 Clock Suspend Mode for READ Cycles Clock suspend mode allows to extend any read burst in progress by a variable number of clock cycles. As long as CKE is registered LOW, the following internal clock pulse(s) will be ignored and data on DQ will remain driven, as shown in Figure 19. FIGURE 19 Clock Suspend Mode for READ Bursts Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 24 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.5.3 READ - DQM Operation DQM may be used to suppress read data and place the output buffers into High-Z state. The generic timing parameters as listed in Table 12 also apply to this DQM operation. The read burst in progress is not affected and will continue as programmed. FIGURE 20 READ Burst - DQM Operation Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 25 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.5.4 READ to WRITE A READ burst may be followed by or truncated with a WRITE command. The WRITE command can be performed to the same or a different (active) bank. Care must be taken to avoid bus contention on the DQs; therefore it is recommended that the DQs are held in High-Z state for a minimum of 1 clock cycle. This can be achieved by either delaying the WRITE command, or suppressing the data-out from the READ by pulling DQM HIGH two clock cycles prior to the WRITE command, as shown in Figure 21. With the registration of the WRITE command, DQM acts as a write mask: when asserted HIGH, input data will be masked and no write will be performed. FIGURE 21 READ to WRITE Timing Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 26 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.5.5 READ to PRECHARGE A READ burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that Auto Precharge was not activated. This is shown in Figure 22. The PRECHARGE command should be issued x clock cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency for READ bursts minus 1. Following the PRECHARGE command, a subsequent ACTIVE command to the same bank cannot be issued until tRP is met. Please note that part of the row precharge time is hidden during the access of the last data elements. In the case of a READ being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same READ burst with Auto Precharge enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate bursts. FIGURE 22 READ to PRECHARGE Timing Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 27 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.6 WRITE FIGURE 23 WRITE Command WRITE bursts are initiated with a WRITE command, as shown in Figure 23. Basic timings for the DQs are shown in Figure 24; they apply to all write operations. The starting column and bank addresses are provided with the WRITE command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the write burst. For the generic WRITE commands used in the following illustrations, Auto Precharge is disabled. FIGURE 24 Basic WRITE Timing Parameters for DQs During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command, and subsequent data elements are registered on each successive positive edge of CLK. Upon completion of a burst, assuming no other commands have been initiated, the DQs remain in High-Z state, and any additional input data is ignored. Figure 25 and Figure 26 show a single WRITE burst for each supported CAS latency setting. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 28 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM TABLE 13 Timing Parameters for WRITE Parameter Symbol min. DQ and DQM input setup time DQ input hold time DQM input hold time DQM write mask latency ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE to PRECHARGE command period WRITE recovery time PRECHARGE command period - 7.5 max. -- -- -- -- -- -- 100k -- -- ns ns ns -- -- -- -- 1) 1) 1) 1) 1) Units Note tIS tIH tDQW tRC tRCD tRAS tWR tRP 1.5 0.8 0.5 0 67 19 45 14 19 tCK ns ns ns ns ns 1) These parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. FIGURE 25 WRITE Burst (CAS Latency = 2) Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 29 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM FIGURE 26 WRITE Burst (CAS Latency = 3) Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. A WRITE command can be issued on any positive edge of clock following the previous WRITE command. The first data element from the new burst is applied after either the last element of a completed burst (Figure 27) or the last desired data element of a longer burst which is being truncated (Figure 28). The new WRITE command should be issued x cycles after the first WRITE command, where x equals the number of desired data elements. FIGURE 27 Consecutive WRITE Bursts Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 30 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM FIGURE 28 Random WRITE Bursts Non-consecutive WRITE bursts are shown in Figure 29. FIGURE 29 Non-Consecutive WRITE Bursts Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 31 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.6.1 WRITE Burst Termination Data from any WRITE burst may be truncated using the BURST TERMINATE command (see Page 36), provided that Auto Precharge was not activated. The input data provided coincident with the BURST TERMINATE command will be ignored. This is shown in Figure 30. The BURST TERMINATE command may be used to terminate a full-page WRITE which does not selfterminate. FIGURE 30 Terminating a WRITE Burst Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 32 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.6.2 Clock Suspend Mode for WRITE Cycles Clock suspend mode allows to extend any WRITE burst in progress by a variable number of clock cycles. As long as CKE is registered LOW, the following internal clock pulse(s) will be ignored and no data will be captured, as shown in Figure 31. FIGURE 31 Clock Suspend Mode for WRITE Bursts Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 33 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.6.3 WRITE - DQM Operation DQM may be used to mask write data: when asserted HIGH, input data will be masked and no write will be performed. The generic timing parameters as listed in Table 13 also apply to this DQM operation. The write burst in progress is not affected and will continue as programmed. FIGURE 32 WRITE Burst - DQM Operation Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 34 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.6.4 WRITE to READ A WRITE burst may be followed by, or truncated with a READ command. The READ command can be performed to the same or a different (active) bank. With the registration of the READ command, data inputs will be ignored and no WRITE will be performed, as shown in Figure 33. FIGURE 33 WRITE to READ Timing 2.4.6.5 WRITE to PRECHARGE A WRITE burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that Auto Precharge was not activated. This is shown in Figure 34. The PRECHARGE command should be issued tWR after the clock edge at which the last desired data element of the WRITE burst was registered. Additionally, when truncating a WRITE burst, DQM must be pulled to mask input data presented during tWR prior to the PRECHARGE command. Following the PRE-CHARGE command, a subsequent ACTIVE command to the same bank cannot be issued until tRP is met. In the case of a WRITE being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same WRITE burst with Auto Precharge enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate bursts. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 35 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM FIGURE 34 WRITE to PRECHARGE Timing 2.4.7 BURST TERMINATE FIGURE 35 BURST TERMINATE Command The BURST TERMINATE command is used to truncate READ or WRITE bursts (with Auto Precharge disabled). The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in Figure 18 and Figure 30, respectively. The BURST TERMINATE command is not allowed for truncation of READ or WRITE bursts with Auto Precharge enabled. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 36 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.8 PRECHARGE FIGURE 36 PRECHARGE Command The PRECHARGE command is used to deactivate (close) the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care". Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. 2.4.8.1 AUTO PRECHARGE Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto Precharge is non persistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 37 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM TABLE 14 Timing Parameters for PRECHARGE Parameter Symbol min. ACTIVE to PRECHARGE command period WRITE recovery time PRECHARGE command period - 7.5 max. 100k -- -- ns ns ns 1) 1) 1) Units Note tRAS tWR tRP 45 14 19 1) These parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. 2.4.8.2 CONCURRENT AUTO PRECHARGE A READ or WRITE burst with Auto Precharge enabled can be interrupted by a subsequent READ or WRITE command issued to a different bank. Figure 37 shows a READ with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge) to bank m. The READ to bank m will interrupt the READ to bank n, CAS latency later. The precharge to bank n will begin when the READ to bank m is registered. Figure 38 shows a READ with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto Precharge) to bank m. The precharge to bank n will begin when the WRITE to bank m is registered. DQM should be pulled HIGH two clock cycles prior to the WRITE to prevent bus contention. Figure 39 shows a WRITE with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge) to bank m. The precharge to bank n will begin tWR after the new command to bank m is registered. The last valid data-in to bank n is one clock cycle prior to the READ to bank m. Figure 40 shows a WRITE with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto Precharge) to bank m. The precharge to bank n will begin tWR after the WRITE to bank m is registered. The last valid data-in to bank n is one clock cycle prior to the WRITE to bank m. FIGURE 37 READ with Auto Precharge Interrupted by READ Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 38 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM FIGURE 38 READ with Auto Precharge Interrupted by WRITE FIGURE 39 WRITE with Auto Precharge Interrupted by READ Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 39 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM FIGURE 40 WRITE with Auto Precharge Interrupted by WRITE 2.4.9 AUTO REFRESH and SELF REFRESH The Mobile-RAM requires a refresh of all rows in a rolling interval. Each refresh is generated in one of two ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode. 2.4.9.1 AUTO REFRESH FIGURE 41 AUTO REFRESH Command AUTO REFRESH is used during normal operation of the Mobile-RAM. The command is non persistent, so it must be issued each time a refresh is required. A minimum row cycle time (tRC) is required between two AUTO REFRESH commands. The same rule applies to any access command after the AUTO REFRESH operation. All banks must be precharged prior to the AUTO REFRESH command. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The Mobile-RAM requires AUTO REFRESH cycles at an average periodic interval of 7.8 s (max.). Partial array mode has no influence on AUTO REFRESH mode. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 40 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM FIGURE 42 Auto Refresh 2.4.9.2 SELF REFRESH FIGURE 43 SELF REFRESH Entry Command The SELF REFRESH command can be used to retain data in the Mobile-RAM, even if the rest of the system is powered down. When in the self refresh mode, the Mobile-RAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is LOW. Input signals except CKE are "Don't Care" during SELF REFRESH. The procedure for exiting SELF REFRESH requires a stable clock prior to CKE returning HIGH. Once CKE is HIGH, NOP commands must be issued for tRC because time is required for a completion of any internal refresh in progress. If during normal operation burst auto refresh or user controlled refresh is used, add 8192 auto refresh cycles just before self refresh entry and just after self refresh exit. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 41 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM FIGURE 44 Self Refresh Entry and Exit TABLE 15 Timing Parameters for AUTO REFRESH and SELF REFRESH Parameter Symbol min. ACTIVE to ACTIVE command period PRECHARGE command period Refresh period (8192 rows) Self refresh exit time - 7.5 max. -- -- 64 -- ns ns ms 1) 1) 1) 1) Units Note tRC tRP tREF tSREX 67 19 -- 1 tCK 1) These parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 42 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.10 POWER DOWN FIGURE 45 Power Down Entry Command Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge powerdown; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CLK and CKE. Power-down duration is limited by the refresh requirements of the device (dddtREF). CKE LOW must be maintained during power-down. The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT command). One clock delay is required for power down entry and exit. FIGURE 46 Power Down Entry and Exit Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 43 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.4.10.1 DEEP POWER DOWN The deep power down mode is an unique function on Low Power SDRAM devices with extremely low current consumption. Deep power down mode is entered using the BURST TERMINATE command (cf. Figure 35) except that CKE is LOW. All internal voltage generators inside the device are stopped and all memory data is lost in this mode. To enter the deep power down mode all banks must be precharged. The deep power down mode is asynchronously exited by asserting CKE HIGH. After the exit, the same command sequence as for power-up initialization, including the 200s initial pause, has to be applied before any other command may be issued (cf. Figure 3 and Figure 4). 2.5 Function Truth Tables This chapter contains the function truth tables. TABLE 16 Current State Bank n - Command to Bank n Current State Any Idle CS H L L L L L Row Active L L L Read L (Auto-Precharge L Disabled) L L Write L (Auto-Precharge L Disabled) L L RAS X H L L L L H H L H H L H H H L H CAS X H H L L H L L H L L H H L L H H WE X H H H L L H L L H L L L H L L L Command / Action DESELECT (NOP / continue previous operation) NO OPERATION (NOP / continue previous operation) ACTIVE (select and activate row) AUTO REFRESH MODE REGISTER SET PRECHARGE READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) READ (select column and start new READ burst) WRITE (select column and start new WRITE burst) PRECHARGE (truncate READ burst, start precharge) BURST TERMINATE READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (truncate WRITE burst, start precharge) Note 1)2)3)4)5)6) 1) to 6) 1) to 6) 1) to 7) 1) to 7) 1) to 6), 8) 1) to 6), 9) 1) to 6), 9) 1) to 6), 10) 1) to 6), 9) 1) to 6), 9) 1) to 6), 10) 1) to 6), 11) 1) to 6), 9) 1) to 6), 9) 1) to 6), 10) 1) 6), 11) BURST TERMINATE 1) This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tRC has been met (if the previous state was self refresh). to 2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3) Current state definitions, see Table 17 4) The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according to Table 20, see also Table 18. 5) The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states, see Table 19 6) All states and sequences not shown are illegal or reserved. 7) Not bank-specific; requires that all banks are idle and no bursts are in progress. 8) Same as NOP command in that state. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 44 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 9) READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and READs or WRITEs with Auto Precharge disabled. 10) May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 11) Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. TABLE 17 Current state definitions Idle Row Active Read Write The bank has been precharged, and tRP has been met A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated TABLE 18 State Definitions 2 Precharging Row Activating Read with AP Enabled Write with AP Enabled Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank is in the "idle" state Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank is in the "row active" state Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state TABLE 19 State Defintions 3 Refreshing Accessing MR Precharging All Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM is in the "all banks idle" state Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the SDRAM is in the "all banks idle" state Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks are in the idle state Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 45 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM TABLE 20 Current State Bank n - Command to Bank m (different bank) Current State Any Idle Row Activating, Active, or Precharging CS H L X L L L L Read (AutoPrecharge Disabled) L L L L Write (AutoPrecharge Disabled) L L L L Read (with AutoPrecharge) L L L L Write (with AutoPrecharge) L L L L RAS X H X L H H L L H H L L H H L L H H L L H H L CAS X H X H L L H H L L H H L L H H L L H H L L H WE X H X H H L L H H L L H H L L H H L L H H L L Command / Action DESELECT (NOP / continue previous operation) NO OPERATION (NOP / continue previous operation) Any command otherwise allowed to bank n ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) Note 1)2)3)4)5)6) 1) to 6) 1) to 6) 1) to 6) 1) to 7) 1) to 7) 1) to 6) 1) to 6) 1) to 7) 1) to 8) 1) to 6) 1) to 6) 1) to 7) 1) to 7) 1) to 6) 1) to 6) 1) to 7), 9) 1) to 9) 1) to 6) 1) to 6) 1) to 7), 9) 1) to 7), 9) 1) to 6) PRECHARGE (deactivate row in bank or banks) 1) This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tRC has been met (if the previous state was Self Refresh). 2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3) Current state definitions, see Table 21 4) AUTO REFRESH, SELF REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle. 5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) All states and sequences not shown are illegal or reserved. 7) READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and READs or WRITEs with Auto Precharge disabled. 8) Requires appropriate DQM masking. 9) Concurrent Auto Precharge: bank n will start precharging when its burst has been interrupted by a READ or WRITE command to bank m. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 46 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM TABLE 21 Current state definitions Idle Row Active Read Write Read with AP Enabled Write with AP Enabled The bank has been precharged, and tRP has been met A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state TABLE 22 Truth Table - CKE CKEn-1 L CKEn L Current State Power Down Self Refresh Clock Suspend Deep Power Down L H Power Down Self Refresh Clock Suspend Deep Power Down H L All Banks Idle Bank(s) Active All Banks Idle Read / Write burst H 1) 2) 3) 4) 5) 6) Command X X X X DESELECT or NOP DESELECT or NOP X X DESELECT or NOP DESELECT or NOP AUTO REFRESH (valid) Action Maintain Power Down Maintain Self Refresh Maintain Clock Suspend Maintain Deep Power Down Exit Power Down Exit Self Refresh Exit Clock Suspend Exit Deep Power Down Enter Precharge Power Down Enter Active Power Down Enter Self Refresh Enter Clock Suspend Note 1)2)3)4) 1) to 4) 1) to 4) 1) to 4) 1) to 4) 1) to 5) 1) to 4) 1) to 4), 6) 1) to 4) 1) to 4) 1) to 4) 1) to 4) 1) to 4) H See Table 16 and Table 20 CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state immediately prior to clock edge n. COMMAND n is the command registered at clock edge n; ACTION n is a result of COMMAND n. All states and sequences not shown are illegal or reserved. DESELECT or NOP commands should be issued on any clock edges occurring during tRC period. Exit from DEEP POWER DOWN requires the same command sequence as for power-up initialization. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 47 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 3 3.1 Electrical Characteristics Operating Conditions TABLE 23 Absolute Maximum Ratings Parameter Symbol min. Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Operation Case Temperature Storage Temperature Power Dissipation Short Circuit Output Current Commercial Extended Values max. 2.7 2.7 V V V V C C C W mA Unit VDD VDDQ VIN VOUT TC TSTG PD IOUT -0.3 -0.3 -0.3 -0.3 0 -25 -55 - - VDDQ + 0.3 VDDQ + 0.3 +70 +85 +150 0.7 50 Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. TABLE 24 Pin Capacitances Parameter Symbol min. Input capacitance: CLK Input capacitance: all other input Input/Output capacitance: DQ Values max. 3.0 3.0 5.0 pF pF pF Unit Note1)2) CI1 CI2 CIO 1.5 1.5 3.0 1) These values are not subject to production test but verified by device characterization. 2) Input capacitance is measured according to JEP147 with VDD, VDDQ applied and all other pins (except the pin under test) floating. DQ's should be in high impedance state. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 48 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM TABLE 25 Electrical Characteristics Parameter Symbol Min. Power Supply Voltage Power Supply Voltage for DQ Output Buffer Input high voltage Input low voltage Output high voltage (IOH = -0.1 mA) Output low voltage (IOL = 0.1 mA) Input leakage current Values Max. 1.95 1.95 V V V V V V - - 2) 2) Unit Note1) Output leakage current -1.5 1.5 A - 1) 0 C TC 70 C (comm.); -25 C TC 85 C (ext.); All voltages referenced to VSS. VSS and VSSQ must be at same potential. 2) VIH may overshoot to VDD + 0.8 V for pulse width < 4 ns; VIL may undershoot to -0.8 V for pulse width < 4 ns. Pulse width measured at 50% with amplitude measured between peak voltage and DC reference level. VDD VDDQ VIH VIL VOH VOL IIL IOL 1.65 1.65 0.8 x VDDQ -0.3 VDDQ + 0.3 0.3 - 0.2 1.0 VDDQ - 0.2 - -1.0 - - - 3.2 AC Characteristics TABLE 26 AC Characteristics Parameter Symbol min. Clock cycle time Clock frequency Access time from CLK Clock high-level width Clock low-level width Address, data and command input setup time Address, data and command input hold time Data (DQ) input hold time MODE REGISTER SET command period DQ low-impedance time from CLK DQ high-impedance time from CLK Data out hold time DQM to DQ High-Z delay (READ Commands) CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 - 7.5 max. -- -- 133 105 5.4 6.0 -- -- -- -- -- -- -- 7.0 -- 2 ns ns ns ns -- -- 7) 7) Unit Note1)2)3)4) tCK fCK tAC tCH tCL tIS tIH tMRD tLZ tHZ tOH tDQZ 7.5 9.5 -- -- -- -- 2.5 2.5 1.5 0.5 0.8 2 1.0 3.0 2.5 -- ns ns MHz MHz ns -- -- 5)6) tCK ns ns ns -- -- -- 5)6) tCK -- Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 49 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM Parameter Symbol min. - 7.5 max. -- -- -- -- 100k -- -- 64 -- Unit Note1)2)3)4) DQM write mask latency ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE bank A to ACTIVE bank B delay ACTIVE to PRECHARGE command period WRITE recovery time PRECHARGE command period Refresh period (8192 rows) Self refresh exit time 1 1) 0 C TC 70 C (comm.); -25 C TC 85 C (ext.); VDD = VDDQ = 1.65V to 1.95V; 2) 3) 4) 5) 6) 7) 8) tDQW tRC tRCD tRRD tRAS tWR tRP tREF tSREX 0 67 19 15 45 14 19 -- tCK ns ns ns ns ns ns ms -- 8) 8) 8) 8) 9) 8) -- -- tCK All parameters assumes proper device initialization. AC timing tests measured at 0.9 V. The transition time tT is measured between VIH and VIL; all AC characteristics assume tT = 1 ns. Specified tAC and tOH parameters are measured with a 30 pF capacity load only as shown in Figure 47. If tT(CLK) > 1 ns, a value of (tT/2 - 0.5) ns has to be added to this parameter. If tT > 1 ns, a value of (tT - 1) ns has to be added to this parameter. These parameter account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period; round up to next integer. 9) The write recovery time of tWR = 14 ns allows the use of one clock cycle for the write recovery time when fCK 72 MHz. With fCK > 72 MHz two clock cycles for tWR are mandatory. Qimonda Technologies recommends to use two clock cycles for the write recovery time in all applications. FIGURE 47 Measurement Conditions for tAC and tOH I/O 30 pF Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 50 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 3.3 Operating Currents TABLE 27 Maximum Operating Currents Parameter & Test Conditions Symbol Values for HY[B/E]... 160B[C/F] - 7.5 Operating current: one bank: active / read / precharge, BL = 1, tRC = tRCmin Precharge power-down standby current: all banks idle, CS VIHmin, CKE VILmax, inputs changing once every two clock cycles Precharge power-down standby current with clock stop: all banks idle, CS VIHmin, CKE VILmax, all inputs stable Precharge non power-down standby current: all banks idle, CS VIHmin, CKE VIHmin, inputs changing once every two clock cycles Precharge non power-down standby current with clock stop: all banks idle, CS VIHmin, CKE VIHmin, all inputs stable Active power-down standby current: one bank active, CS VIHmin, CKE VILmax, inputs changing once every two clock cycles Active power-down standby current with clock stop: one bank active, CS VIHmin, CKE VILmax, all inputs stable Active non power-down standby current: one bank active, CS VIHmin, CKE VIHmin, inputs changing once every two clock cycles Active non power-down standby current with clock stop: one bank active, CS VIHmin, CKE VIHmin, all inputs stable Operating burst read current: all banks active; continuous burst read, inputs changing once every two clock cycles Auto-Refresh current: tRC = tRCmin, "burst refresh", inputs changing once every two clock cycles Values for HYE... 160B[C/F]L - 7.5 60 0.4 mA mA 2)3) Unit Note1) IDD1 IDD2P 60 0.6 2) IDD2PS IDD2N 0.5 13 0.35 13 mA mA - 2) IDD2NS IDD3P 1.0 1.0 1.0 1.0 mA mA - 2) IDD3PS IDD3N 0.75 15 0.5 15 mA mA - 2) IDD3NS IDD4 1.5 45 1.5 45 mA mA - 2)3) IDD5 90 90 mA 2) Self Refresh current: IDD6 self refresh mode, CS VIHmin, CKE VILmax, all inputs stable See Table 28 20 A - - Recommended Operating Conditions unless otherwise noted 2) These values are measured with tCK = 7.5 ns 3) All parameters are measured with no output loads. IDD7 20 Deep Power Down current 1) 0 C TC 70 C (comm.); -25 C TC 85 C (ext.); VDD = VDDQ = 1.65V to 1.95V; Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 51 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM TABLE 28 Self Refresh Currents Parameter & Test Conditions Max. Symbol Values for Values for Temperature HY[B/E]256160B[C/F] HYE256160B[C/F]L typ. Self Refresh Current: Self refresh mode, full array activation (PASR = 000) Self Refresh Current: Self refresh mode, half array activation (PASR = 001) Self Refresh Current: Self refresh mode, quarter array activation (PASR = 010) 85 C 70 C 45 C 25 C 85 C 70 C 45 C 25 C 85 C 70 C 45 C 25 C max. 600 - - - 470 - - - 400 - - - typ. 430 285 190 175 305 220 155 140 245 180 135 120 - - - 320 - - - 260 - - - max. 450 A Units Note1)2) IDD6 510 340 225 205 400 285 200 180 340 250 185 170 1) 0 C TC 70 C (comm.); -25 C TC 85 C (ext.); VDD = VDDQ = 1.65V to 1.95V 2) The On-Chip Temperature Sensor (OCTS) adjusts the refresh rate in self refresh mode to the component's actual temperature with a much finer resolution than supported by the 4 distinct temperature levels as defined by JEDEC for TCSR. At production test the sensor is calibrated, and IDD6 max. current is measured at 85C. Typ. values are obtained from device characterization. Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 52 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 3.4 Pullup and Pulldown Characteristics TABLE 29 Half Drive Strength and Full Drive Strength Voltag e (V) Half Drive Strength Pull-Down Current (mA) Nominal Low 0.00 0.40 0.65 0.85 1.00 1.40 1.50 1.65 1.80 1.95 0.0 15.1 20.3 22.0 22.6 23.5 23.6 23.8 23.9 24.0 Nominal High 0.0 20.5 28.5 32.0 33.5 35.0 35.3 35.5 35.7 35.9 Pull-Up Current (mA) Nominal Low -19.7 -18.8 -18.2 -17.6 -16.7 -9.4 -6.6 -1.8 3.8 9.8 Nominal High -33.4 -32.0 -31.0 -29.9 -28.7 -20.4 -17.1 -11.4 -4.8 2.5 Full Drive Strength Pull-Down Current (mA) Nominal Low 0.0 30.2 40.5 43.9 45.2 46.9 47.2 47.5 47.7 48.0 Nominal High 0.0 41.0 57.0 64.0 67.0 70.0 70.5 71.0 71.4 71.8 Pull-Up Current (mA) Nominal Low -39.3 -37.6 -36.4 -35.1 -33.3 -18.8 -13.2 -3.5 7.5 19.6 Nominal High -66.7 -63.9 -61.9 -59.8 -57.3 -40.7 -34.1 -22.7 -9.6 5.0 The above characteristics are specified under nominal process variation / condition Temperature (Tj): Nominal = 50 C, VDDQ: Nominal = 1.80 V Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 53 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 4 Package Outlines FIGURE 48 P-VFBGA-54-2 (Plastic Thin Fine Ball Grid Array Package) 8 x 0.8 = 6.4 0.8 0.12 +0.01 -0.04 0.3 D 8 x 0.8 = 6.4 D 1.7 0.03 0.8 5) 205 B 4) 2) A 4) 3) 1) 0.1 C 1.0 -0.2 0.1 C 0.310.03 0.41 0.03 54x o0.12 o0.07 M M C AB 1.5 2) C SEATING PLANE 4.25 0.2 2.24 12 1) A1 Marking Ballside 2) Die Sort Fiducial 3) Bad Unit Marking (BUM) 4) Middle of Packages Edges 5) Middle of Ball Matrix Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 54 8 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Standard Ballout 256-Mbit Mobile-RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Power-Up Sequence and Mode Register Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Address / Command Inputs Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 No operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Mode Register Set Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Mode Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ACTIVE command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bank Activate Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Basic READ Timing Parameters for DQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Single READ Burst (CAS Latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Single READ Burst (CAS Latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Random READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Non-Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Clock Suspend Mode for READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 READ Burst - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 READ to WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 READ to PRECHARGE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Basic WRITE Timing Parameters for DQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WRITE Burst (CAS Latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 WRITE Burst (CAS Latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Consecutive WRITE Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Random WRITE Bursts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Non-Consecutive WRITE Bursts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Clock Suspend Mode for WRITE Bursts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 WRITE Burst - DQM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 WRITE to READ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 WRITE to PRECHARGE Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 BURST TERMINATE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 READ with Auto Precharge Interrupted by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 READ with Auto Precharge Interrupted by WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 WRITE with Auto Precharge Interrupted by READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 WRITE with Auto Precharge Interrupted by WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 AUTO REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 SELF REFRESH Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Self Refresh Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Power Down Entry Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Power Down Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Measurement Conditions for tAC and tOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 P-VFBGA-54-2 (Plastic Thin Fine Ball Grid Array Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 55 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM Table of Contents 1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.2.1 2.2.1.1 2.2.1.2 2.2.1.3 2.2.1.4 2.2.1.5 2.2.1.6 2.2.1.7 2.2.1.8 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.5.1 2.4.5.2 2.4.5.3 2.4.5.4 2.4.5.5 2.4.6 2.4.6.1 2.4.6.2 2.4.6.3 2.4.6.4 2.4.6.5 2.4.7 2.4.8 2.4.8.1 2.4.8.2 2.4.9 2.4.9.1 2.4.9.2 2.4.10 2.4.10.1 2.5 3 3.1 3.2 3.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 4 5 6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Partial Array Self Refresh (PASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Temperature Compensated Self Refresh (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Selectable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MODE REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 READ Burst Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Clock Suspend Mode for READ Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 READ - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WRITE Burst Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Clock Suspend Mode for WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 WRITE - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CONCURRENT AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AUTO REFRESH and SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DEEP POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 48 49 51 Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 56 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 3.4 4 Pullup and Pulldown Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Rev. 1.73, 2006-09 01302004-CZ2R-J9SE 57 Data Sheet Edition 2006-09 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Under no circumstances may the Qimonda product as referred to in this Data Sheet be used in 1. Any applications that are intended for military usage (including but not limited to weaponry), or 2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or (ii) Cause the failure of such Critical Systems; or b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or (ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to property, whether tangible or intangible). www.qimonda.com |
Price & Availability of HYB18L256160BC-75
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